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While NoCs gained recently a significant momentum, there are few NoC implementations of real applications reported to date.

Other relevant bibliographies:

In this chapter, we present an MPEG-2 encoder using the NoC approach and compare it against the P2P and non-segmented bus-based designs running the same application. The MPEG-2 encoder has been selected as driver application since it covers a rich class of multimedia applications where similar considerations apply from an implementation standpoint.

This chapter provides an overview of the network-on-chip architecture and application models utilized in this book. We first describe the target NoC platform and list our basic assumptions.


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Then, we present the NoC architecture and application models employed throughout the book. Finally, we conclude this chapter by discussing the technology implications on networks-on-chip design.

On-Chip Networks

Traditionally, performance evaluation of networks-on-chip NoC is largely based on simulation which, besides being extremely slow, provides little insight on how different design parameters can affect the actual network performance. Therefore, it is practically impossible to use simulation for optimization purposes. This chapter presents a mathematical model for on-chip routers and utilize this new model for NoC performance analysis. The model presented in this chapter can be used not only to obtain fast and accurate performance estimates, but also to guide the NoC design process within an optimization loop.

The accuracy of our approach and its practical use is illustrated through extensive simulation results. Networks-on-chip NoC represent a promising solution to complex on-chip communication problems. The NoC communication architectures considered in the literature are based on either completely regular or fully customized topologies.

On Modeling, Analysis, and Optimization of Packet Aggregation Systems

This chapter presents a methodology to automatically synthesize an architecture which is neither regular, nor fully customized. Instead, the resulting communication architecture is a superposition of a standard mesh network and a few long-range links which induce small world effects. Indeed, the few application-specific longrange links we insert significantly increase the critical traffic workload at which the network transitions from a free to a congested state.

This way, we can exploit the benefits offered by both complete regularity and partial topology customization.

Publications

While networks-on-Chip NoC architectures may offer higher bandwidth compared to traditional bus-based communication, their performance can degrade significantly in the absence of effective flow control algorithms. This chapter presents a predictive closed-loop flow control mechanism, which is used to predict the congestion level in the network. Based on this information, the proposed scheme controls the packet injection rate at traffic sources in order to regulate the total number of packets in the network.

Finally, simulations and experimental study using our FPGA prototype show that the proposed controller delivers a better performance compared to the traditional switch-to-switch flow control algorithms under various real and synthetic traffic patterns. The design of many core systems-on-chip SoCs has become increasingly challenging due to high levels of integration, excessive energy consumption, and clock distribution problems. To deal with these issues, this chapter considers network-on-chip NoC architectures partitioned into several voltage-frequency islands VFIs and propose a design methodology for runtime energy management.


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The proposed approach minimizes the energy consumption subject to performance constraints. Here at Walmart. Your email address will never be sold or distributed to a third party for any reason.

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Book Format: Choose an option. Product Highlights Traditionally, design space exploration for Systems-on-Chip SoCs has focused on the computational aspects of the problem at hand. However, as the number of components on a single chip and their performance continue to increase, the communication architecture plays a major role in the area, perform.

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